Freescale Semiconductor /MKW20Z4 /XCVR /TSM_TIMING10

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Interpret as TSM_TIMING10

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_VCO_BUF_RX_EN_RX_HI 0PLL_VCO_BUF_RX_EN_RX_LO

Description

TSM_TIMING10

Fields

PLL_VCO_BUF_RX_EN_RX_HI

Assertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence.

PLL_VCO_BUF_RX_EN_RX_LO

Deassertion time setting for PLL_VCO_BUF_RX_EN signal or group RX sequence.

Links

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